A Wideband Low-Power Cascade ∑∆ Modulator Based on Considerations of the Integrator Settling Behavior

This paper presents a study of the effect of settling error due to finite gain-bandwidth product (GBW) and slew-rate (SR) of opamps in SC Σ∆ A/D modulators. Based on the theoretical point of view, a new architecture for cascade multibit Σ∆ A/D modulators is proposed to achieve better performances at low oversampling ratio. The performance improvement is analyzed and compared with traditional cascade architectures. Simulation results show that the proposed Sigma-Delta modulator relaxes the circuit requirement on the GBW of opamps up to twice the sampling frequency. At the same time, the requirement on slew rate is significantly low, so that it can be automatically satisfied for an adequate settle during its settling phase. Therefore, the proposed architecture is suitable for wideband and low-power applications. Moreover, it is shown that the proposed architecture is also immune to other non-idealities, such as finite DC-gain, capacitor mismatching and non-linear DC-gain. Key-Words: Analog integrated circuits, high-speed high-resolution analog–to-digital converters, and sigma–delta modulator